A fully-pipeline linear systolic architecture for modular multiplier in public-key crypto-systems

DOI10.1023/A:1021110405895zbMath1039.68173MaRDI QIDQ1405485

Xingjun Wu, Weixin Gai, Yihe Sun, Hong-Yi Chen

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

zbMATH Keywords

systolic arraypipeline architecturemodular-exponentiationmodular-multiplicationpublic-key crypto-system

Mathematics Subject Classification ID

Cryptography (94A60) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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