High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

DOI10.1023/A:1022123829466zbMath1039.68049OpenAlexW1598107865MaRDI QIDQ1405490

Bart Vanhoof, Roberto R. Osorio

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1022123829466

zbMATH Keywords

arithmetic codingentropy coding

Mathematics Subject Classification ID

Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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