Low power synthesis methodology with data format optimization applied on a DWT

DOI10.1023/A:1023660801499zbMath1039.68170OpenAlexW1552342889MaRDI QIDQ1405544

D. Massart

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1023660801499

zbMATH Keywords

discrete wavelet transformlow powerdesign methodologypower optimizationreal time systemdata formatdedicated architecturehigh level synthesis

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)