VLSI architecture of modified Euclidean algorithm for Reed-Solomon code.

DOI10.1016/S0020-0255(03)00154-3zbMath1038.94015OpenAlexW2066760909MaRDI QIDQ1425296

D. Massart

Publication date: 15 March 2004

Published in: Information Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0020-0255(03)00154-3

zbMATH Keywords

Reed-Solomon codeEuclidean algorithmVLSI architecturedecoding algorithmBerlekamp's key equationError correcting code

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Reliability, testing and fault tolerance of networks and computer systems (68M15) Decoding (94B35) Multiplicative structure; Euclidean algorithm; greatest common divisors (11A05)

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Cites Work

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• Inversionless decoding of both errors and erasures of Reed-Solomon code
• On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm
• Transform Techniques for Error Control Codes
• A design of Reed-Solomon decoder with systolic-array structure