Formal verification of a complex pipelined processor

DOI10.1023/A:1024716316140zbMath1057.68062OpenAlexW1861031206MaRDI QIDQ1426941

Ganesh Gopalakrishnan, Mandayam Srivas, Ravi Hosabettu

Publication date: 15 March 2004

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1024716316140

zbMATH Keywords

formal verificationPVScompletion functionsprocessor verification

Mathematics Subject Classification ID

Abstract data types; algebraic specification (68Q65)

Related Items (1)

Algebraic models of behaviour and correctness of SMT and CMT processors

Uses Software

• PVS

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