BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

DOI10.1007/BF02960763zbMath1095.68544MaRDI QIDQ1433981

Hafizur Rahaman, Debesh K. Das, Bhargab Bikram Bhattacharya

Publication date: 1 July 2004

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
• Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks
• Syndrome-Testable Design of Combinational Circuits
• Transition Count Testing of Combinational Logic Circuits
• Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

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