A methodology for hardware verification using compositional model checking
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Publication:1566919
DOI10.1016/S0167-6423(99)00030-1zbMath0954.68005OpenAlexW2054198444MaRDI QIDQ1566919
Publication date: 4 June 2000
Published in: Science of Computer Programming (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/s0167-6423(99)00030-1
Related Items (6)
Partial Order Reduction for Deep Bug Finding in Synchronous Hardware ⋮ A mechanism of function calls in MSVL ⋮ Mind the Shapes: Abstraction Refinement Via Topology Invariants ⋮ Exploring structural symmetry automatically in symbolic trajectory evaluation ⋮ Verifying Reference Counting Implementations ⋮ Temporal prophecy for proving temporal properties of infinite-state systems
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