Formal verification of masked hardware implementations in the presence of glitches

DOI10.1007/978-3-319-78375-8_11zbMath1428.94062OpenAlexW2795180100MaRDI QIDQ1648840

Johannes Winter, Stefan Mangard, Rinat Iusupov, Roderick Bloem, Bettina Könighofer, Hannes Gross

Publication date: 9 July 2018

Full work available at URL: https://doi.org/10.1007/978-3-319-78375-8_11

zbMATH Keywords

formal verificationmaskingside-channel analysishardware securityprivate circuitsthreshold implementations

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Related Items (7)

Towards tight random probing security ⋮ Proving SIFA protection of masked redundant circuits ⋮ Effective and efficient masking with low noise using small-Mersenne-prime ciphers ⋮ Handcrafting: improving automated masking in hardware with manual optimizations ⋮ Secure and efficient software masking on superscalar pipelined processors ⋮ SILVER -- statistical independence and leakage verification ⋮ Fast verification of masking schemes in characteristic two

Uses Software

• z3
• EasyCrypt
• REBECCA
• Yosys
• acrt

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