A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

DOI10.1007/s00607-016-0535-4zbMath1381.68043OpenAlexW2570152998WikidataQ57592850 ScholiaQ57592850MaRDI QIDQ1700863

Vasilios Kelefouras

Publication date: 22 February 2018

Published in: Computing (Search for Journal in Brave)

Full work available at URL: http://eprints.whiterose.ac.uk/113153/7/review_ver4.pdf

zbMATH Keywords

cachedata reuseloop tilingregister allocationloop transformationsiterative compilationloop unrollscalar replacement

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20)

Uses Software

• ATLAS

Cites Work

• Adaptive optimizing compilers for the 21st century
• Optimal register allocation for SSA-form programs in polynomial time
• A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
• Data Structures and Algorithms
• Automated empirical optimizations of software and the ATLAS project
• Unnamed Item

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