Fault-tolerant design of a shift register at the nanoscale based on quantum-dot cellular automata

DOI10.1007/S10773-018-3781-8zbMath1412.81085OpenAlexW2803698771WikidataQ57777980 ScholiaQ57777980MaRDI QIDQ1740880

Nima Jafari Navimipour, Sonia Afrooz

Publication date: 3 May 2019

Published in: International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10773-018-3781-8

zbMATH Keywords

multiplexerfault-tolerantquantum-dot cellular automata (QCA)universal shift register

Mathematics Subject Classification ID

Quantum computation (81P68) Cellular automata (computational aspects) (68Q80) Mathematical problems of computer architecture (68M07) Reliability, testing and fault tolerance of networks and computer systems (68M15) Quantum algorithms and complexity in the theory of computing (68Q12) Quantum dots, waveguides, ratchets, etc. (81Q37)

Related Items (3)

Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing ⋮ A new coplanar design of multiplier based on nanoscale quantum-dot cellular automata ⋮ An optimized three-level design of decoder based on nanoscale quantum-dot cellular automata

Uses Software

• QCADesigner

Cites Work

• Implementing a one-bit reversible full adder using quantum-dot cellular automata
• An optimized three-level design of decoder based on nanoscale quantum-dot cellular automata
• Designing nanoscale counter using reversible gate based on quantum-dot cellular automata
• A three-layer full adder/subtractor structure in quantum-dot cellular automata
• A novel design of 8-bit adder/subtractor by quantum-dot cellular automata
• Adder and Multiplier Design in Quantum-Dot Cellular Automata

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