Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption

DOI10.1007/978-3-319-71667-1_15zbMath1421.94059OpenAlexW2770824113MaRDI QIDQ1746847

Anupam Chattopadhyay, Mustafa Khairallah, Thomas Peyrin

Publication date: 26 April 2018

Full work available at URL: https://doi.org/10.1007/978-3-319-71667-1_15

zbMATH Keywords

FPGAauthenticated encryptionAESLEDDeoxyslogic optimizationtechnology mapping

Mathematics Subject Classification ID

Cryptography (94A60) Authentication, digital signatures and secret sharing (94A62)

Related Items (1)

The \texttt{Deoxys} AEAD family

This page was built for publication: Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption