Mapping matrix multiplication algorithm onto fault-tolerant systolic array

DOI10.1016/J.CAMWA.2002.12.016zbMath1063.65032OpenAlexW2006182245MaRDI QIDQ1767936

T. I. Tokić, N. M. Stojanović, Ivan Stojmenović, Emina I. Milovanović, Igor Ž. Milovanović

Publication date: 8 March 2005

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.camwa.2002.12.016

zbMATH Keywords

Numerical examplesFault-toleranceMatrix multiplicationSystolic arraysVLSI/WSI algorithms

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Related Items (1)

A class of fault-tolerant systolic arrays for matrix multiplication

Cites Work

• The design of optimal planar systolic arrays for matrix multiplication
• Algorithm-Based Fault Tolerance for Matrix Operations
• Design of space-optimal regular arrays for algorithms with linear schedules
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