Processor-efficient sparse matrix-vector multiplication

DOI10.1016/j.camwa.2003.06.009zbMath1069.65048OpenAlexW2153830704MaRDI QIDQ1767967

Lenwood S. Heath, Calvin J. Ribbens, Sriram V. Pemmaraju

Publication date: 8 March 2005

Published in: Computers \& Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.camwa.2003.06.009

zbMATH Keywords

algorithmssystolic arrayssparse matricesmatrix-vector multiplicationstaircase width

Mathematics Subject Classification ID

Related Items (2)

FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method ⋮ The Local Queue Number of Graphs with Bounded Treewidth

Uses Software

• LAPACK
• SparseMatrix
• ILUM

Cites Work

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