Debugging VHDL designs: Introducing multiple models and first empirical results
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Publication:1768500
DOI10.1023/B:APIN.0000033635.98612.1EzbMath1075.68576OpenAlexW2084302879MaRDI QIDQ1768500
Publication date: 15 March 2005
Published in: Applied Intelligence (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1023/b:apin.0000033635.98612.1e
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