Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices

DOI10.1134/S0005117918040082zbMath1437.94105OpenAlexW2796769915MaRDI QIDQ1796241

V. V. Sapozhnikov, Vl. V. Sapozhnikov, V. V. Dmitriev, D. V. Efanov

Publication date: 17 October 2018

Published in: Automation and Remote Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s0005117918040082

zbMATH Keywords

concurrent error detectionBerger codecombinational devicedata vectorproperties of error detectionsum code

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Related Items (1)

Synthesis of self-checking combination devices based on allocating special groups of outputs

Cites Work

• Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits
• Summation codes for organization of control of combinational circuits
• On summation code properties in functional control circuits
• Checking of combinational circuits basing on modification sum codes
• A t-unidirectional error-detecting systematic code
• Study of combinational self-checking devices with independent and monotonic independent outputs
• A modified summation code for organizing control of combinatorial circuits
• On codes with summation of data bits in concurrent error detection systems
• New structures of the concurrent error detection systems for logic circuits
• Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
• A note on error detection codes for asymmetric channels

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