Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

DOI10.1016/0020-0190(93)90203-LzbMath0770.68063OpenAlexW2085287525MaRDI QIDQ1802064

V. P. Muthuswamy, P. Thangavel

Publication date: 20 September 1993

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(93)90203-l

zbMATH Keywords

addition of two \(n\)-bit numbersmultiplication of two \(n\)-bit binary numbersPARBS

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Distributed algorithms (68W15)

Related Items (2)

Integer summing algorithms on reconfigurable meshes ⋮ Scaling multiple addition and prefix sums on the reconfigurable mesh.

Cites Work

• Constant time sorting on a processor array with a reconfigurable bus system
• Fast one's-complement multiplication
• A Two's Complement Parallel Array Multiplication Algorithm
• Algorithms for Iterative Array Multiplication
• A Way to Build Efficient Carry-Skip Adders
• A Regular Layout for Parallel Adders
• Combinational Circuit Synthesis with Time and Component Bounds
• A Compact High-Speed Parallel Multiplication Scheme

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