Reconfigurable systolic arrays with fixed size and structure degradation

DOI10.1007/BF01124999zbMath0875.68562MaRDI QIDQ1816311

V. S. Kharchenko, V. G. Litvinenko, V. A. Krasnobayev

Publication date: 14 January 1997

Published in: Cybernetics and Systems Analysis (Search for Journal in Brave)

zbMATH Keywords

reconfiguration algorithmsself-testing processorsVLSI systolic arrays

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Unnamed Item

This page was built for publication: Reconfigurable systolic arrays with fixed size and structure degradation