Trace theory and VLSI design

zbMath0616.68001MaRDI QIDQ1821550

Jan L. A. van de Snepscheut

Publication date: 1985

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

zbMATH Keywords

program representationformal languagesconcurrencyregular languagestraceshardware implementationVLSI chipscomplexity of program designdelay-insensivityhardware realization of programsminimization of finite automata

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Circuits, networks (94C99) Algebraic theory of languages and automata (68Q70) Research exposition (monographs, survey articles) pertaining to computer science (68-02) General topics in the theory of software (68N01)

Related Items (14)

An alternative implementation of communication primitives ⋮ Infinite unfair shuffles and associativity ⋮ Computing and the cultures of proving ⋮ Compiling communicating processes into delay-insensitive VLSI circuits ⋮ On the existence of delay-insensitive fair arbiters: Trace theory and its limitations ⋮ Deadlock and fairness in morphisms of transition systems ⋮ Correctness of concurrent processes ⋮ Locked discrete event systems: How to model and how to unlock ⋮ Progress assumption in concurrent systems ⋮ Receptive process theory ⋮ Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench ⋮ Delay-insensitivity and ternary simulation ⋮ Synchronized shuffles ⋮ A formal approach to designing delay-insensitive circuits

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