A two-layered mesh array for matrix multiplication

DOI10.1016/0167-8191(88)90078-6zbMath0683.65024OpenAlexW1975458934MaRDI QIDQ1824984

Subhash C. Kak

Publication date: 1988

Published in: Parallel Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-8191(88)90078-6

zbMATH Keywords

systolic arraymatrix multiplicationarray of processorscylindrical array

Mathematics Subject Classification ID

Related Items (4)

N latency 2N I/O‐bandwidth 2D‐array matrix multiplication algorithm ⋮ Multilayered array computing ⋮ Orthogonal residue sequences ⋮ Mapping full‐systolic arrays for matrix product on XILINX's XC4000(E,EX) FPGAs

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