A 16-bit by 16-bit MAC design using fast 5:3 compressor cells

DOI10.1023/A:1015333103608zbMATH Open1003.68601OpenAlexW1834244558MaRDI QIDQ1851142

Earl E. jun. Swartzlander, Kevin Nowka, Oh Sang Kwon

Publication date: 15 December 2002

Published in: Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1015333103608

zbMATH Keywords

multiplierMAC3:2 counter4:2 compressor5:2 compressor5:3 compressor

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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