Performance-scalable array architectures for modular multiplication

DOI10.1023/A:1015337204517zbMATH Open1014.68235OpenAlexW3157432466MaRDI QIDQ1851147

William L. Freking, Keshab K. Parhi

Publication date: 15 December 2002

Published in: Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1015337204517

zbMATH Keywords

pipelined architecturessystolic computationhigh-radix arithmetic implementationmodular multipliers

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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