PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators

DOI10.1023/A:1015341305426zbMath1006.68689OpenAlexW2109876904MaRDI QIDQ1851159

Darren Cronquist, Robert Schreiber, Mukund Sivaraman, Shail Aditya, Vinod Kathail, B. Ramakrishna Rau, Scott A. Mahlke

Publication date: 15 December 2002

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1015341305426

zbMATH Keywords

automatic parallelizationdatapath synthesishigh-level hardware synthesis

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems

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