Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks

DOI10.1023/A:1015452903532zbMath1041.68009OpenAlexW1867684417MaRDI QIDQ1851173

Yanyan Li

Publication date: 15 December 2002

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1015452903532

zbMATH Keywords

buffer minimizationdataflow graphsDigital Signal Processing (DSP) computationMulti-Rate Software PipeliningRegular Stream Flow Graphs,software pipelining

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Related Items (1)

Complexity results for weighted timed event graphs

This page was built for publication: Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks