A statement based parallelizing framework for processor-in-memory architectures

DOI10.1016/S0020-0190(02)00353-8zbMath1011.68501OpenAlexW2025763027MaRDI QIDQ1853696

Slo-Li Chu, Tsung-Chuan Huang

Publication date: 22 January 2003

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0020-0190(02)00353-8

zbMATH Keywords

schedulingSAGEparallelizing compilerFlexRAMprocessor-in-memorystatement analysis

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cites Work

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