Intermediate representations for design automation of multiprocessor DSP systems

DOI10.1023/A:1020307222052zbMath1035.68561OpenAlexW1491546977MaRDI QIDQ1857127

Vida Kianzad, Mukul Khandelia, Shuvra S. Bhattacharyya, Neal Bambha

Publication date: 17 February 2003

Published in: Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1020307222052

zbMATH Keywords

embedded systemsdigital signal processinginterprocessor communicationDataflow graphsself-timed scheduling

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) General topics in the theory of software (68N01)

Related Items (1)

Self-timed scheduling analysis for real-time applications

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