Compilation from Matlab to process networks realized in FPGA

DOI10.1023/A:1020367508848zbMath1035.68610OpenAlexW2114317MaRDI QIDQ1857137

Richard Walke, Tim Harriss, Bart Kienhuis, E. F. A. Deprettere

Publication date: 17 February 2003

Published in: Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1020367508848

zbMATH Keywords

FPGAMatlabskewingnested loop programsProcess networksstream-based model of computationunrolling

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) General topics in the theory of software (68N01)

Related Items (2)

Requirements for interfacing IP-components in re-configurable platforms ⋮ Multidimensional DSP core synthesis for FPGA

Uses Software

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