Performance evaluation and optimal design for FPGA-based digit-serial DSP functions

DOI10.1016/S0045-7906(01)00043-XzbMath1006.68616MaRDI QIDQ1860067

Hanho Lee, Gerald E. Sobelman

Publication date: 20 February 2003

Published in: Computers and Electrical Engineering (Search for Journal in Brave)

zbMATH Keywords

arithmeticFIR filtermultiplierdigital signal processingfield programmable gate arrayadderdigit serial

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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