Static analysis for state-space reductions preserving temporal logics

DOI10.1023/B:FORM.0000033963.55470.9ezbMath1073.68055OpenAlexW2010609147MaRDI QIDQ1878929

Karen Yorav, Orna Grumberg

Publication date: 9 September 2004

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/b:form.0000033963.55470.9e

zbMATH Keywords

static analysis(partially) dead variable reductionpath reductiontemporal logic preservation

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30)

Related Items (6)

State space reduction for process algebra specifications ⋮ On partial state matching ⋮ Application of static analyses for state-space reduction to the microcontroller binary code ⋮ Formal communication elimination and sequentialization equivalence proofs for distributed system models ⋮ State Space Reduction of Linear Processes Using Control Flow Reconstruction ⋮ Formal Sequentialization of Distributed Systems via Program Rewriting

Uses Software

• veriSoft

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