A partitioning methodology that optimises the area on reconfigurable real-time embedded systems

DOI10.1155/S1110865703212051zbMATH Open1089.68502WikidataQ57831927 ScholiaQ57831927MaRDI QIDQ1886897

Serge Weber, Philippe Brunet, Yves Berviller, Camel Tanougast

Publication date: 19 November 2004

Published in: EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

zbMATH Keywords

partitioningimplementationFPGAreconfigurable systems on chip

Mathematics Subject Classification ID

Computing methodologies for image processing (68U10) Mathematical problems of computer architecture (68M07)

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