An FPGA implementation of \((3,6)\)-regular low-density parity-check code decoder

DOI10.1155/S1110865703212105zbMath1089.68503OpenAlexW2165573644MaRDI QIDQ1886906

Keshab K. Parhi, Tong Zhang

Publication date: 19 November 2004

Published in: EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1155/s1110865703212105

zbMATH Keywords

decoderFPGAlow-density parity-check codeserror-correcting coding

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Decoding (94B35)

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