A methodology for rapid prototyping peak-constrained least-squares bit-serial finite impulse response filters in FPGAs

DOI10.1155/S1110865703301015zbMath1089.93522MaRDI QIDQ1886909

Laurence E. Turner, Trevor W. Fox, Alex Carreira

Publication date: 19 November 2004

Published in: EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

zbMATH Keywords

mappingFIR filterplacementbit serialJBitsPCLS

Mathematics Subject Classification ID

Filtering in stochastic control theory (93E11) Digital control/observation systems (93C62)

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