Harmonic buffer management policy for shared memory switches

DOI10.1016/J.TCS.2004.05.014zbMath1072.68007OpenAlexW2074950314MaRDI QIDQ1887082

Alexander Kesselman, Yishay Mansour

Publication date: 23 November 2004

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.tcs.2004.05.014

zbMATH Keywords

Competitive analysisBuffer managementNon-preemptive policiesShared memory switches

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Distributed systems (68M14)

Related Items (8)

Essential Traffic Parameters for Shared Memory Switch Performance ⋮ The network as a storage device: dynamic routing with bounded buffers ⋮ Better bounds for online \(k\)-frame throughput maximization in network switches ⋮ Tight Analysis of Priority Queuing for Egress Traffic ⋮ Improved competitive performance bounds for CIOQ switches ⋮ Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing ⋮ Competitive buffer management for multi-queue switches in QoS networks using packet buffering algorithms ⋮ Admission control in shared memory switches

Cites Work

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• Competitive queue policies for differentiated services
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• Buffer Management in a Packet Switch
• Competitive buffer management for shared-memory switches
• Buffer overflow management in QoS switches
• Optimal smoothing schedules for real-time streams (extended abstract)
• On-line load balancing with applications to machine scheduling and virtual circuit routing

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