Graph partitioning applied to the logic testing of combinational circuits
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Publication:1900143
DOI10.1016/0166-218X(94)00150-CzbMath0833.68093MaRDI QIDQ1900143
Madlaine Davis-Moradkhan, Catherine Roucairol
Publication date: 17 October 1995
Published in: Discrete Applied Mathematics (Search for Journal in Brave)
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Related Items (4)
A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits ⋮ PO-MOESP subspace identification of directed acyclic graphs with unknown topology ⋮ Partitioning \(P_4\)-tidy graphs into a stable set and a forest ⋮ Effects of adding a reverse edge across a stem in a directed acyclic graph
Cites Work
- Verification Testing—A Pseudoexhaustive Test Technique
- Logic Test Pattern Generation Using Linear Codes
- Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
- A class of combinatorial problems with polynomially solvable large scale set covering/partitioning relaxations
- LSI logic testing — An overview
- The Weighted Syndrome Sums Approach to VLSI Testing
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