A hierarchical block-floating-point arithmetic

DOI10.1023/A:1008110410087zbMath0955.68003OpenAlexW1589910777MaRDI QIDQ1974486

Shiro Kobayashi, Gerhard P. Fettweis

Publication date: 7 May 2000

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1008110410087

zbMATH Keywords

DSP architecturesmobile communication

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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