Combined asynchronous/synchronous packet switching architecture: QoS guarantees for integrated parallel computing and real-time traffic

DOI10.1006/JPDC.1999.1607zbMath0958.68502OpenAlexW1989391255MaRDI QIDQ1974674

Publication date: 7 May 2000

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1006/jpdc.1999.1607

zbMATH Keywords

quality of service

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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