Formal specification and verification of dynamic parametrized architectures

DOI10.1007/978-3-319-95582-7_37zbMath1460.68056OpenAlexW2809414477MaRDI QIDQ2024379

Ivan Stojic, Stefano Tonetta, Alessandro Cimatti

Publication date: 4 May 2021

Full work available at URL: https://doi.org/10.1007/978-3-319-95582-7_37

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items

Verification of SMT systems with quantifiers, Unnamed Item, SMT-based verification of data-aware processes: a model-theoretic approach, Universal invariant checking of parametric systems with quantifier-free SMT reasoning

Cites Work

• Unnamed Item
• Unnamed Item
• A calculus of mobile processes. I
• Backward Reachability of Array-based Systems by SMT solving: Termination and Invariant Synthesis
• Towards the Verification of Attributed Graph Transformation Systems
• Handbook of Graph Grammars and Computing by Graph Transformation
• Parameterized Systems in BIP: Design and Model Checking
• A Theory Agenda for Component-Based Design
• Behaviour, Interaction and Dynamics
• MCMT: A Model Checker Modulo Theories