On checking equivalence of simulation scripts

DOI10.1016/j.jlamp.2021.100640OpenAlexW3122374654MaRDI QIDQ2035653

Igor Melatti, Federico Mari, Toni Mancini, Enrico Tronci, Annalisa Massini

Publication date: 25 June 2021

Published in: Journal of Logical and Algebraic Methods in Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jlamp.2021.100640

zbMATH Keywords

formal verificationsystem-level formal verificationformal verification of cyber-physical systemssimulation based formal verification

Mathematics Subject Classification ID

Computer science (68-XX)

Related Items (1)

Editorial: Tribute to Anna Labella

Uses Software

• PHAVer
• HyTech
• StateFlow
• Uppaal
• Dymola
• AutoMOTGen
• S-TaLiRo
• dReach
• DryVR

Cites Work

• Unnamed Item
• Unnamed Item
• On minimising the maximum expected verification time
• HyTech: A model checker for hybrid systems
• Simulation-equivalent reachability of large linear systems with inputs
• Bayesian statistical model checking with application to Stateflow/Simulink verification
• Model-based testing of reactive systems. Advanced lectures.
• Towards a UTP Semantics for Modelica
• S-TaLiRo: A Tool for Temporal Logic Falsification for Hybrid Systems
• Mutation-Based Test Case Generation for Simulink Models
• Numerical nonlinear regulator design
• Linearizing Discrete-Time Hybrid Systems
• SyLVaaS: System Level Formal Verification as a Service*
• Fundamental Approaches to Software Engineering
• Hybrid Systems: Computation and Control
• On simulation-based probabilistic model checking of mixed-analog circuits

This page was built for publication: On checking equivalence of simulation scripts