A novel parallel prefix adder for optimized radix-2 FFT processor

DOI10.1007/s11045-021-00772-1OpenAlexW3138303626MaRDI QIDQ2044538

Garima Thakur, Shruti Jain, Harsh Sohal

Publication date: 9 August 2021

Published in: Multidimensional Systems and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11045-021-00772-1

zbMATH Keywords

FFT algorithmPP addersradix 2 structureWallace multiplier

Mathematics Subject Classification ID

Computer aspects of numerical algorithms (65Yxx)

Cites Work

• An efficient design for reversible Wallace unsigned multiplier
• Parallel Prefix Computation
• A Regular Layout for Parallel Adders
• A Reduced Complexity Wallace Multiplier Reduction
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
• Majority Gate Networks

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