Constructing a sequence detecting robustly testable path delay faults in sequential circuits

DOI10.1134/S0005117921110102zbMath1497.94207OpenAlexW4200413702MaRDI QIDQ2069707

E. A. Nikolaeva, A. Yu. Matrosova, O. Kh. Kim, S. V. Chernyshov

Publication date: 21 January 2022

Published in: Automation and Remote Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s0005117921110102

zbMATH Keywords

homing sequencereduced ordered binary decision diagram (ROBDD)rising (falling) transitionrobustly testable path delay fault (PDF)sequential logic circuit

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Cites Work

• Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

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