Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths

DOI10.1016/j.dam.2021.12.007OpenAlexW4220747421MaRDI QIDQ2074348

Jannik Silvanus, Anna Silvanus, Ulrich Brenner

Publication date: 9 February 2022

Published in: Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/2012.05550

zbMATH Keywords

adder circuitsand-or pathsdepth optimization

Mathematics Subject Classification ID

Theory of computing (68Qxx) Circuits, networks (94Cxx) Boolean algebras (Boolean rings) (06Exx)

Uses Software

• JBool
• OEIS

Cites Work

• Fast prefix adders for non-uniform input arrival times
• Delay optimization of linear depth Boolean circuits with prescribed input arrival times
• Size-depth tradeoff in non-monotone Boolean formulae
• Size-depth tradeoff in monotone Boolean formulae
• The delay of circuits whose inputs have specified arrival times
• Monotone Circuits for Connectivity Require Super-Logarithmic Depth
• Parallel Prefix Computation
• Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
• Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times
• On the Addition of Binary Numbers
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
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