Improving the LUT count for mealy FSMS with transformation of output collections

DOI10.34768/AMCS-2022-0035OpenAlexW4391126140MaRDI QIDQ2099308

Małgorzata Mazurkiewicz, Larysa Titarenko, Alexander Barkalov

Publication date: 23 November 2022

Published in: International Journal of Applied Mathematics and Computer Science (Search for Journal in Brave)

Full work available at URL: https://doaj.org/article/f091f5a9df254d51b501f3e1ae4b38da

zbMATH Keywords

synthesisFPGALUTmealy FSMstate codes

Mathematics Subject Classification ID

Computer system organization (68Mxx) Circuits, networks (94Cxx) Computer science (68-XX)

Related Items (2)

Binary associative memories with complemented operations ⋮ Technology mapping of multi-output functions leading to the reduction of dynamic power consumption in FPGAs

Uses Software

• ABC

Cites Work

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• Hardware reduction for LUT-based Mealy FSMs
• Improving characteristics of LUT-based Mealy FSMs
• Embedded System Design

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