Integrating side channel security in the FPGA hardware design flow

DOI10.1007/978-3-030-68773-1_13OpenAlexW3127222271MaRDI QIDQ2106708

Davide Zoni, Alessandro Barenghi, William Fornaciari, Matteo Brevi, Gerardo Pelosi

Publication date: 16 December 2022

Full work available at URL: https://doi.org/10.1007/978-3-030-68773-1_13

zbMATH Keywords

side channel analysisdesign automation and toolsFPGA design flow

Mathematics Subject Classification ID

Cryptography (94A60) Computer science (68-XX)

Uses Software

• GitHub
• Yosys
• SymbiFlow

Cites Work

• Unnamed Item
• GitHub
• Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software
• Mutual information analysis: a comprehensive study
• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

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