Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder
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Publication:2111000
DOI10.1007/s11128-022-03754-9OpenAlexW4312014124WikidataQ116846679 ScholiaQ116846679MaRDI QIDQ2111000
Valentina Ciriani, L. Kettunen, Majid Haghparast, Asma Taheri Monfared
Publication date: 23 December 2022
Published in: Quantum Information Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s11128-022-03754-9
Cites Work
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- Radix-independent, efficient arrays for multi-level \(n\)-qudit quantum and reversible computation
- Controlled gates for multi-level quantum computation
- On figures of merit in reversible and quantum logic designs
- Towards quantum reversible ternary coded decimal adder
- Constructing all qutrit controlled Clifford+\(T\) gates in Clifford+\(T\)
- Quaternary quantum/reversible half-adder, full-adder, parallel adder and parallel adder/subtractor circuits
- A normal form for single-qudit Clifford+\(T\) operators
- Towards designing quantum reversible ternary multipliers
- Optimized parity preserving quantum reversible full adder/subtractor
- NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS
- NOVEL QUANTUM COMPRESSOR DESIGNS USING NEW GENETIC ALGORITHM-BASED SIMULATOR, ANALYZER AND SYNTHESIZER SOFTWARE IN NANOTECHNOLOGY
- MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
- Irreversibility and Heat Generation in the Computing Process
- Generating the group of reversible logic gates
- Ternary logic design in topological quantum computing
- Quantum Cryptography with 3-State Systems
- Quaternary regenerative CMOS logic circuits with high-impedance output state
- Logical Reversibility of Computation
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