Timed Petri nets with reset for pipelined synchronous circuit design
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Publication:2117152
DOI10.1007/978-3-030-76983-3_4zbMath1489.68166OpenAlexW3172377947MaRDI QIDQ2117152
Rémi Parrot, Mikaël Briday, Olivier H. Roux
Publication date: 21 March 2022
Full work available at URL: https://doi.org/10.1007/978-3-030-76983-3_4
Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Networks and circuits as models of computation; circuit complexity (68Q06)
Related Items (3)
Waiting nets ⋮ Design and verification of pipelined circuits with timed Petri nets ⋮ Waiting Nets: State Classes and Taxonomy
Cites Work
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- Complexity results for 1-safe nets
- Model-checking in dense real-time
- Retiming synchronous circuitry
- A theory of timed automata
- The expressive power of time Petri nets
- Time and Petri Nets
- TCTL Model Checking of Time Petri Nets
- Properties and performance bounds for timed marked graphs
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