Protecting secure ICs against side-channel attacks by identifying and quantifying potential EM and leakage hotspots at simulation stage

DOI10.1007/978-3-030-89915-8_6zbMath1491.94063OpenAlexW3208976711MaRDI QIDQ2145294

Thomas Ordas, Philippe Maurine, Davide Poggi, Alexandre Sarafianos

Publication date: 17 June 2022

Full work available at URL: https://doi.org/10.1007/978-3-030-89915-8_6

zbMATH Keywords

simulationEM side-channel analysissecure IC design

Mathematics Subject Classification ID

Cryptography (94A60)

Cites Work

• A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
• Cryptographic Hardware and Embedded Systems - CHES 2004
• Unnamed Item
• Unnamed Item
• Unnamed Item

This page was built for publication: Protecting secure ICs against side-channel attacks by identifying and quantifying potential EM and leakage hotspots at simulation stage