A HDL generator for flexible and efficient finite-field multipliers on FPGAs

DOI10.1007/978-3-030-68869-1_4OpenAlexW3132421755MaRDI QIDQ2232211

Joël Cathébras, Roselyne Chotin

Publication date: 4 October 2021

Full work available at URL: https://doi.org/10.1007/978-3-030-68869-1_4

zbMATH Keywords

design space explorationfinite-field multiplierFPGA design

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Cites Work

• Guide to FPGA implementation of arithmetic functions
• Architecture level optimizations for Kummer based HECC on FPGAs
• (Leveled) fully homomorphic encryption without bootstrapping
• A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over $$\mathrm{GF}(p)$$
• Modular Multiplication Without Trial Division
• Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

This page was built for publication: A HDL generator for flexible and efficient finite-field multipliers on FPGAs