A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

DOI10.1007/s11432-009-0024-xzbMath1192.68609OpenAlexW2080624378MaRDI QIDQ2267141

Zhizhong Tang, Dong-Sheng Wang, Tian Song

Publication date: 26 February 2010

Published in: Science in China. Series F (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11432-009-0024-x

zbMATH Keywords

network securitypattern matchingnetwork intrusion detectionnetwork intrusion prevention

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10)

Related Items

A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

Uses Software

• Snort

Cites Work

• A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
• A fast string searching algorithm
• Efficient string matching
• Fast Pattern Matching in Strings