ASIC implementation of area-efficient, high-throughput 2-D IIR filter using distributed arithmetic

DOI10.1007/S00034-017-0698-ZzbMath1411.94111OpenAlexW2767213351MaRDI QIDQ2312516

Prashant Kumar, Prabhat Chandra Shrivastava, Manish K. Tiwari, Amit Dhawan

Publication date: 17 July 2019

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-017-0698-z

zbMATH Keywords

VLSI designraster scanningdistributed arithmetic2-D IIR filterhardware-based LUTmultiplier-less filters

Mathematics Subject Classification ID

Filtering in stochastic control theory (93E11) Analytic circuit theory (94C05)

Related Items (1)

Design and implementation of low complexity circularly symmetric 2D FIR filter architectures

Cites Work

• Unnamed Item
• FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic
• A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm

This page was built for publication: ASIC implementation of area-efficient, high-throughput 2-D IIR filter using distributed arithmetic