Decimal square root: algorithm and hardware implementation

DOI10.1007/S00034-015-0215-1zbMath1367.65224OpenAlexW2281729759MaRDI QIDQ2362598

Adel Hosseiny, Ghassem Jaberipur

Publication date: 10 July 2017

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-015-0215-1

zbMATH Keywords

decimal arithmeticdecimal square rootdigit recurrencequotient digit selection

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) General topics in the theory of algorithms (68W01) Numerical algorithms for computer arithmetic, etc. (65Y04)

Uses Software

• CUDA

Cites Work

• A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
• Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems
• High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
• High Speed Decimal Addition

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