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Hierarchical circuit comparison as a top-down VLSI design verification technique - MaRDI portal

Hierarchical circuit comparison as a top-down VLSI design verification technique

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Publication:2366261

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zbMath0825.94256MaRDI QIDQ2366261

Krzysztof Woźniakowski, Mariusz Niewczas

Publication date: 29 June 1993

Published in: Bulletin of the Polish Academy of Sciences. Technical Sciences (Search for Journal in Brave)

Mathematics Subject Classification ID

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